1. Field of the Invention
The present invention relates to a pattern correction apparatus, a pattern optimization apparatus, and an integrated circuit design apparatus for correcting, optimizing, and designing a pattern of an integrated circuit.
2. Description of the Related Art
With a leap progress in LSI manufacturing techniques, an ultrafine process called deep submicron has been used. From a physical viewpoint, further miniaturization a process poses difficulty in designing a layout. Moreover, in relation to a signal delay (a gate delay or a trace delay), the influence of a trace delay becomes greater, and hence a contrivance to trace design is required.
In association with the shorter life of LSI products, yields of the LSI manufacturing technique must be enhanced immediately. For instance; in order to realize a design for simpler production, a commitment to a DFM (Design For Manufacturing) technique is sought. Improvements in design quality and reductions in fraction defective are sought not only in the field of LSIs for use in automobiles but also in the field of consumer-oriented or industrial LSIs.
What greatly affects a trace delay as a result of a reduction in the minimum pitch between wires associated with recent miniaturization is crosstalk. A principle approach for avoiding occurrence of crosstalk is a reduction in inter-trace capacitance and asynchronous switching among adjacent wires. A method for increasing a trace pitch is available for reducing inter-trace capacitance. For example, in connection with layout data acquired after detailed routing, a trace pitch disregarding trace grids is enlarged by use of an automatic layout tool.
Next, a finer design rule poses extreme difficulty in mask processing, which in turn raises a problem of deteriorated yields and a failure to manufacture an LSI at worst. These problems are attributable to a graphics pattern of a semiconductor mask being finer than the wavelength of light used for exposure. Further, at some locations, the problems are attributable to a layout relationship between wires and vias. For example, when denseness and nondenseness are present in the pattern, it may be the case where a pattern cannot be transferred accurately.
Although degeneration failure or open failure is detected by use of a test pattern, detecting all nodes is difficult to perform. There is the possibility of a short circuit or a break arising between traces as a result of minute dust or extraneous matters having adhering to nodes (undetected nodes) that cannot be detected by means of the test pattern, to thus cause product deficiency.
An example of the technique for creating a layout pattern which is intended for reducing the chance of occurrence of a cross talk in an LSI or enhancing yields is described in JP-A-2005-301799. Correction of a layout of a pattern of an integrated circuit will be described briefly by reference to FIG. 28.
As shown in FIG. 28, a method for correcting a pattern of an integrated circuit comprises selecting an arbitrary trace pattern by means of taking, as an input, pattern information (21-1) which is an aggregate of trace patterns (step 21-2); computing the degree of adjacent balance from inter-trace capacitance between a trace pattern R selected in step 21-2 and a trace pattern adjacent to the trace pattern R (step 21-3); and moving the position of an adjacent trace pattern in accordance with the degree of adjacent balance computed in step 21-3 (step 21-4).
According to the above method, an adjacent trace pattern is moved in accordance with the degree of adjacent balance determined from inter-trace capacitance developing between a selected trace pattern and an adjacent trace pattern, so that a trace pitch can be increased when compared with a trace pitch determined by the original trace pattern. Therefore, optimization of timing of an LSI chip and realization of a layout which diminishes crosstalk are possible, and yields can be enhanced.                Patent Document 1: JP-A-2005-301799        
However, under the previously described method for correcting a pattern of an integrated circuit, when a necessity for correcting a trace pattern after optimization of a trace pitch has arisen, it is difficult to correct a trace which is not present on any trace grid by use of an automatic routing tool. Even if correction of the trace is feasible, enormous time is consumed. Further, an evaluation function does not include vias, it may be the case where yields are reduced by means of denseness and nondenseness of the graphics pattern. In association with further miniaturization of a process in future, denseness and nondenseness of a graphics pattern pertaining to vias must also be taken into consideration.
Moreover, a fraction defective in the market (hereinafter called a “market fraction defective”) is computed from the rate of detection of degeneration failures acquired by use of a test pattern. However, in association with miniaturization of a process, a market fraction defective cannot be ascertained by means of a parameter including only the rate of detection of failures determined through use of a test pattern. Further, since graphic pattern information is not included in parameters used for computing a fraction defective, graphics pattern correction for diminishing a market fraction defective cannot be made.